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US 2013/0154708 A1Published application
Configurable flip-flop
AssigneeFreescale Semiconductor, Inc.
InventorsShayan Zhang, Ravindraraj Ramaraju
Life of this patent
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Abstract
A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal.
Claims20
A device comprising a flip-flop, the flip-flop comprising:
- a clock input;
- a first flush control input;
- a data input;
- and
- a data output, the flip-flop configured to:
- when a first flush control signal at the flush control input is negated, latch data present at the data input in response to assertion of a clock signal at the clock input;
- and
- when the first flush control signal is asserted, buffer data present at the data input independent of the clock signal at the clock input.
5 more elements
A flip-flop comprising:
- an data input;
- a master stage;
- and
- a slave stage;
- the flip-flop configured to, in a first mode of operation, latch data present at the data input at a master stage of the flip-flop based on a clock signal and configured to, in a second mode of operation, buffer data at the data input at the master stage independent of the clock signal.
2 more elements
A method, comprising:
- in response to determining a flip-flop is in a first mode of operation, latching data at a master stage of the flip-flop based on a clock signal;
- and
- in response to determining the flip-flop is in a second mode of operation, buffering data at the master stage of the flip-flop independent of the clock signal.
Dependencies are inferred from the claim text.