Duty cycle correction circuit and delay locked loop circuit including the same

A duty cycle correction circuit comprising:

• a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal;
• a duty cycle detection unit configured to detect a duty cycle of the output clock and generate a detection voltage and an up-down signal;
• a voltage detection unit configured to generate an input noise signal according to the level of the detection voltage;
• a noise detection signal generation unit configured to detect a variation of the input noise signal and generate a noise detection signal;
• and
• a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.

A delay locked loop (DLL) circuit comprising:

• a variable delay unit configured to adjust a delay amount of an external clock signal according to a phase detection signal and output a DLL clock signal;
• a delay model unit configured to receive the DLL clock signal and generate a feedback clock signal by delaying the DLL clock signal by a model delay value;
• a feedback phase comparison unit configured to compare phases of the feedback clock signal and the external clock signal and generate the phase detection signal according to a comparison result;
• a detection unit configured to generate an up-down signal by detecting a duty cycle of the DLL clock signal, and generate a noise detection signal by detecting a variation in duty cycle of the DLL clock signal;
• a duty cycle correction control unit configured to generate a duty cycle correction code in response to the noise detection signal and the up-down signal;
• and
• a duty cycle correction unit configured to correct a duty cycle of the external clock signal according to the duty cycle correction code.

A DLL circuit comprising:

• a variable delay unit configured to adjust a delay amount of an external clock signal according to a phase detection signal and output a DLL clock signal;
• a delay model unit configured to receive the DLL clock signal and generate a feedback clock signal by delaying the DLL clock signal by a model delay value;
• a feedback phase comparison unit configured to compare phases of the feedback clock signal and the external clock signal and generate the phase detection signal according to the comparison result;
• a duty cycle detection unit configured to detect a duty cycle of the DLL clock and generate a detection voltage and an up-down signal;
• a voltage detection unit configured to generate an input noise signal according to the level of the detection voltage;
• a noise detection signal generation unit configured to detect a variation of the input noise signal and generate a noise detection signal;
• a duty cycle correction control unit configured to generate a duty cycle correction code in response to the noise detection signal and the up-down signal;
• and
• a duty cycle correction unit configured to correct a duty cycle of the external clock signal according to the duty cycle correction code.