Phase-locked loop frequency stepping

A method, implemented by a phase-locked loop (PLL), comprising:

• incrementing or decrementing a first frequency division value from a current feedback divider value to a desired feedback divider value;
• modulating the first frequency division value to produce a second frequency division value;
• and
• dividing the frequency of an input clock signal by the second frequency division value to produce an output clock signal.

A computer system comprising:

• a phase-locked loop (PLL) comprising:
• a ramp generator for providing a modulator with a first frequency division value, wherein the ramp generator increments or decrements the first frequency division value from a current feedback divider value to a desired feedback divider value;
• a modulator for modulating the first frequency division value to produce a second frequency division value;
• and
• a frequency divider for dividing the frequency of an input clock signal by the second frequency division value to produce an output clock signal.

A computer-readable storage medium storing a set of instructions used for manufacturing a device including a phase-lock loop (PLL), the set of instructions comprising:

• an incrementing or decrementing code segment for incrementing or decrementing a first frequency division value from a current feedback divider value to a desired feedback divider value;
• a modulating code segment for modulating the first frequency division value to produce a second frequency division value;
• and
• a dividing code segment for dividing the frequency of an input clock signal by the second frequency division value to produce an output clock signal.