Multi-phase clock generation apparatus and method
AssigneeIntel Corporation
InventorsShenggao Li, Roan M. Nicholson
Life of this patent
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Abstract
A multi-phase clock generator may receive an input clock signal as an input. The clock generator may also receive an inverse of the input clock signal. The clock generator may produce a plurality of output clock signals having different phases. The phases of the output clock signals may be evenly spaced. The output clock signals may have a similar waveform to the input clock signal, with a frequency that is lower than the input clock signal by a division factor.
Claims24
A clock generation apparatus, comprising:
- a plurality of stages arranged in a ring with an output terminal of each stage coupled to an input terminal of a next stage at an output node, each stage configured to receive complementary input clock signals at respective first and second clock terminals and to receive a prior output signal from a prior stage at the input terminal and produce an output signal at the output terminal that is an inverted and delayed version of the prior output signal;
- and
- a plurality of latch structures, each latch structure being configured to cause an output signal at a respective output node to be the inverse of another output signal at a respective other output node;
- wherein the output signals at each output node have different phases.
A method of clock generation, comprising:
- receiving a first input clock signal at a first clock terminal of a first stage, the first stage being one of a plurality of stages arranged in a ring with an output terminal of each stage coupled to an input terminal of a next stage at an output node;
- receiving a second input clock signal at a second clock terminal of the first stage;
- receiving, at a first input terminal of the first stage, a first output clock signal;
- and
- outputting a second output clock signal at a first output terminal of the first stage, the second output clock signal having a logical level that is an inverse of a logical level of the first output clock signal if the first input clock signal has a first logic state;
- wherein output clock signals at different output nodes of the ring are inverses of one another.
A computing system, comprising:
- a microprocessor having one or more processor cores, at least one of the processor cores including an eight-phase clock generator having:
- eight stages arranged in a ring with an output terminal of each stage coupled to an input terminal of a next stage at an output node, each stage configured to receive complementary input clock signals at respective first and second clock terminals and to produce an output signal at the output terminal that is a delayed and inverted version of an input signal at the input terminal;
- and
- a plurality of latch structures, each latch structure coupled between a pair of output nodes positioned halfway around the ring from one another, the latch structure configured to cause output clock signals at the pair of output nodes to be inverses of one another.
A clock generation apparatus, comprising:
- a plurality of output nodes;
- a plurality of stages arranged in a ring, each stage including an inverter and a transmission gate and coupled to a next stage at a corresponding output node;
- and
- one or more pairs of cross-coupled inverters, the cross-coupled inverters coupled between opposing pairs of output nodes on the ring.
Dependencies are inferred from the claim text.