Boolean logic in a state machine lattice
AssigneeMicron Technology, Inc.
InventorsHarold B Noyes, David R. Brown, Paul Glendenning, Irene J. Xu
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorsHarold B Noyes, David R. Brown, Paul Glendenning, Irene J. Xu
Estimating the term…
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.
A device, comprising:
A method of performing a logic operation at a Boolean logic cell in a state machine lattice, the method comprising:
(canceled)
A method of programming a Boolean logic cell in a state machine lattice, the method comprising programming the Boolean logic cell to perform a particular logic function of a plurality of programmable logic functions, wherein the Boolean logic cell comprises a mask input configured to receive a masking input signal that masks the input of the Boolean logic cell.
A Boolean logic cell configured to be selectively coupled to programmable elements in a state machine lattice, wherein the Boolean logic cell is configured to receive inputs from outputs of the programmable elements selectively coupled thereto and to be programmable to perform a selected logic function of a plurality of possible logic functions on the inputs, wherein the Boolean logic cell is further configured to:
(canceled)
Dependencies are inferred from the claim text.