Method for packaging semiconductors at a wafer level
AssigneeRaytheon Company
InventorsRobert B. Hallock, William J. Davis, Yiwen Zhang, Ward G. Fillmore, Susan C. Trulli, Jason G. Milne
Life of this patent
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Abstract
A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.
Claims20
A method is provided for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer, comprising:
- forming device exposing openings and electrical contact exposing opening in a dielectric layer disposed on the surface portion of the semiconductor wafer to expose the devices and electrical contacts pads, respectively;
- and
- depositing a porous material in the device exposing openings over the devices.
A package for a semiconductor device formed in a surface portion of a semiconductor wafer, the package comprising:
- a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad;
- and
- a porous material in the device exposing opening over said one of the devices.
A package for a semiconductor device formed in a surface portion of a semiconductor wafer, comprising:
- a first dielectric layer comprising a first lithographically processable material disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad such one of the devices;
- and
- a porous material in the device exposing opening over said one of the devices;
- and
- a second dielectric layer comprising a second lithographically processable material disposed on the porous material and on selected regions of the first dielectric layer and absent from the electrical contacts pad opening of the first dielectric layer.
Dependencies are inferred from the claim text.