Method of lowering capacitances of conductive apertures and an interposer capable of being reverse biased to achieve reduced capacitance

A three dimensional integrated circuit, comprising:

• a first die;
• a second die;
• and
• an interposer capable of being reversed bias located between said first and said second die and configured to connect said first die to said second die, said interposer including:
• a semiconductor substrate that is doped with a dopant;
• conductive paths located within said semiconductor substrate and configured to provide electrical routes through said semiconductor to connect said first die to said second die;
• and
• an ohmic contact region located within said semiconductor substrate and adapted to be coupled to a back bias voltage source.

A method of manufacturing an interposer capable of being reversed biased, comprising:

• providing a doped semiconductor substrate of an interposer, said doped semiconductor substrate including at least one conductive path;
• heavily doping a region of said doped semiconductor substrate to form an ohmic contact region;
• and
• forming a metallic contact near a surface of said doped semiconductor substrate in electrical contact with said ohmic contact region.