Chip package and method for forming the same
AssigneeXintec Inc.
InventorsKuo-Hua LIU, Yi-Ming CHANG, Hsi-Chien LIN
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AssigneeXintec Inc.
InventorsKuo-Hua LIU, Yi-Ming CHANG, Hsi-Chien LIN
Estimating the term…
A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.
A chip package, comprising:
A chip package, comprising:
A method for forming a chip package, comprising:
Dependencies are inferred from the claim text.