Packaged leadless semiconductor device

A method of packaging a semiconductor die comprising:

• providing a heat sink flange having an upper surface and a lower surface spaced apart by a flange thickness;
• attaching said semiconductor die to said upper surface of said flange;
• providing a frame structure having a perimeter that defines a cavity and terminal pads surrounding said cavity, said frame structure being pre-formed to include bent ones of said terminal pads, each of said terminal pads including a first surface and a second surface, said first surface being spaced apart from said second surface by a distance that is greater than said flange thickness;
• mechanically staking said frame structure to said heat sink flange such that at least a portion of said first surface of said each terminal pad overlies said upper surface of said heat sink flange and such that said lower surface of said heat sink flange and said second surface of said each of said terminal pads are in coplanar alignment;
• electrically connecting said semiconductor die with said first surface of said terminal pads using interconnects;
• and
• encasing said flange, said frame structure, said semiconductor die, and said interconnects in an encapsulant wherein at least said lower surface of said heat sink flange and said second surface of said each of said terminal pads remain exposed from said encapsulant.

A packaged leadless semiconductor device comprising:

• a heat sink flange having an upper surface and a lower surface spaced apart by a flange thickness, said flange thickness being at least thirty mils;
• a semiconductor die physically coupled to said upper surface of said heat sink flange;
• a frame structure having a perimeter that defines a cavity and terminal pads surrounding said cavity, each of said terminal pads including a folded arrangement having a first section, a second section, and a connector section interconnecting said first and second sections, wherein a first surface is formed on a top side of said first section, and a second surface is formed on an underside of said second section, said first surface being spaced apart from said second surface by a distance that is at greater than said flange thickness, and said heat sink flange is positioned in said cavity such that said lower surface of said heat sink flange and said second surface of each of said terminal pads are in coplanar alignment, and at least a portion of said first surface of said each of said terminal pads overlies said upper surface of said heat sink flange;
• interconnects electrically connecting said semiconductor die with said first surface of said terminal pads;
• and
• an encapsulant encasing said frame structure, said flange, said semiconductor die, and said interconnects with at least said lower surface of said heat sink flange and said second surface of said each of said terminal pads remaining exposed from said encapsulant.