Capacitor and register of semiconductor device, memory system including the semiconductor device, and method of manufacturing the semiconductor device

A register of a semiconductor device, comprising:

• a register structure on which edge regions each stepwise patterned and a central region disposed between the edge regions are defined, and configured to comprise register layers and interlayer insulating layers alternately stacked;
• sacrificial layers disposed within the respective register layers in the edge regions of the register structure;
• and
• support plugs formed in the central region of the register structure and configured to penetrate the register layers and the interlayer insulating layers.

A method of forming a capacitor of a semiconductor device;

• the method comprising:
• forming a capacitor structure on which edge regions each stepwise patterned and a central region between the edge regions are defined, and configured to comprise sacrificial layers and dielectric layers alternately stacked and support plugs placed in the central region;
• forming first slits, each placed between the support plugs of the central region, and one or more second slits placed in the edge regions by etching the sacrificial layers and the dielectric layers;
• etching the sacrificial layers exposed in the first slits and the second slits so that the sacrificial layers of the central region are fully removed and the sacrificial layers of the edge regions remain partially;
• and
• forming electrode layers for the capacitor by filling the etched regions of the sacrificial layers with a conductive layer.

A method of forming a register of a semiconductor device;

• the method comprising:
• forming a register structure configured to comprise sacrificial layers and interlayer insulating layers alternately stacked, support plugs placed in a central region, and edge regions each stepwise patterned;
• forming first slits, each placed between the support plugs of the central region, and one or more second slits placed in the edge regions by etching the sacrificial layers and the interlayer insulating layers;
• etching the sacrificial layers exposed in the first slits and the second slits so that the sacrificial layers of the central region are fully removed and the sacrificial layers of the edge regions remain partially;
• and
• forming register layers by filling the etched regions of the sacrificial layers with a conductive layer.