Semiconductor device isolation structures
AssigneeMicron Technology, Inc.
InventorSukesh Sandhu
Life of this patent
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Abstract
Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a substrate that is spaced apart from a first integrated device region. An isolation region may be interposed between the first integrated device region and the second integrated device region. The isolation region may include an isolation recess that projects into the substrate to a first predetermined depth, and that may be extended to a second predetermined depth.
Claims20
A semiconductor memory device, comprising:
- a memory array region comprising a device recess;
- an isolation region including an isolation recess adjacent to the memory array region;
- and
- a dielectric filler fully filling the isolation recess and partially filling the device recess.
A processing system, comprising:
- a central processing unit (CPU);
- and
- a memory device operatively coupled to the CPU by a communications bus, wherein the memory device includes:
- a memory array region comprising a device recess;
- an isolation region adjacent to the memory array region, the memory array region including an isolation recess extending to a first depth;
- and
- a dielectric filler fully filling the isolation recess and partially filling the device recess.
A semiconductor memory device, comprising:
- an isolation region adjacent to a memory array region comprising a device recess, the isolation region including an isolation recess that includes a first interior wall portion covered by a conformal dielectric;
- and
- an extended recess including a second interior wall portion and a floor portion, the second interior wall portion and the floor portion of the extended recess being substantially covered by a second dielectric that is different from the conformal dielectric.
Dependencies are inferred from the claim text.