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US 2013/0154024 A1Published application
Structure and method of latchup robustness with placement of through wafer via within cmos circuitry
AssigneeInternational Business Machines Corporation
InventorsPhillip F. CHAPMAN, David S. COLLINS, Steven H. VOLDMAN
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Abstract
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
Claims10
A semiconductor structure, comprising:
- an NFET device having a P-well at a top side of a substrate;
- a PFET device having an N-well at the top side of the substrate;
- and
- a substrate contact comprising a through wafer via extending from a backside of the substrate to a bottom surface of an isolation structure located between the NFET device and the PFET device,
- wherein the substrate contact is arranged to prevent formation of a parasitic circuit.
2 more elements
A semiconductor structure, comprising:
- an NFET device having a P-well at a top side of a substrate;
- a PFET device having an N-well at the top side of the substrate;
- a deep well formed in the substrate below the N-well and the P-well;
- a through wafer via extending from a backside of the substrate to a bottom surface of an isolation structure;
- an electrical connection region between the through wafer via and the deep well;
- and
- a high voltage junction between the through wafer via and the substrate.
4 more elements
Dependencies are inferred from the claim text.