SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, SRAM, AND METHOD FOR PRODUCING Dt-MOS TRANSISTOR

A static random access memory, comprising:

• a first CMOS inverter including a first MOS transistor forming a channel of a first conductivity type and a second MOS transistor forming a channel of a second conductivity type that is opposite to the first conductivity type, the first MOS transistor and the second MOS transistor being connected in series via a first node;
• a second CMOS inverter including a third MOS transistor forming a channel of the second conductivity type and a fourth MOS transistor forming a channel of the first conductivity type, the third MOS transistor and the fourth MOS transistor being connected in series via a second node, the first CMOS inverter and the second CMOS inverter forming a flip-flop circuit;
• a first transfer transistor connected between a first bit line and the first node and including a first gate electrode connected to a word line, the first transfer transistor being driven by a selection signal on the word line;
• and
• a second transfer transistor connected between a second bit line and the second node and including a second gate electrode connected to the word line, the second transfer transistor being driven by a selection signal on the word line, wherein
• the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the first transfer transistor, and the second transfer transistor are formed on a common silicon substrate;
• a first element region for the first MOS transistor and the first transfer transistor, a second element region for the second MOS transistor, a third element region for the third MOS transistor, and a fourth element region for the fourth MOS transistor and the second transfer transistor are defined in the silicon substrate by an element isolation region;
• a first contact region having the second conductivity type and disposed adjacent to the first element region and a second contact region having the second conductivity type and disposed adjacent to the fourth element region are defined in the silicon substrate by the element isolation region;
• the first element region includes a first well with the second conductivity type;
• the fourth element region includes a second well with the second conductivity type;
• the first transfer transistor includes
• a first gate electrode formed on the silicon substrate via a first gate insulating film and extending from the first element region to a first sub-region of the element isolation region between the first element region and the first contact region,
• a first source diffusion region having the first conductivity type and formed in the first well, and
• a first drain diffusion region having the first conductivity type and formed in the first well,
• a first insulating region formed in the silicon substrate and disposed to contact a lower end of the first source diffusion region, and
• a second insulating region formed in the silicon substrate and disposed to contact a lower end of the first drain diffusion region;
• the second transfer transistor includes
• a second gate electrode formed on the silicon substrate via a second gate insulating film and extending from the fourth element region to a second sub-region of the element isolation region between the fourth element region and the second contact region,
• a second source diffusion region having the first conductivity type and formed in the second well, and
• a second drain diffusion region having the first conductivity type and formed in the second well,
• a third insulating region formed in the silicon substrate and disposed to contact a lower end of the second source diffusion region, and
• a fourth insulating region formed in the silicon substrate and disposed to contact a lower end of the second drain diffusion region;
• the first well is disposed below the first gate electrode between the first insulating region and the second insulating region;
• the second well is disposed below the second gate electrode between the third insulating region and the fourth insulating region;
• the first well extends below the first sub-region and is electrically connected with the first contact region;
• the second well extends below the second sub-region and is electrically connected with the second contact region;
• upper ends of the first and second insulating regions are located higher than a lower end of the first well;
• upper ends of the third and fourth insulating regions are located higher than a lower end of the second well;
• lower ends of the first and second insulating regions are located lower than the lower end of the first well;
• lower ends of the third and fourth insulating regions are located lower than the lower end of the second well;
• a lower end of the element isolation region except the first and second sub-regions is located lower than the lower ends of the first, second, third, and fourth insulating regions;
• the first sub-region is in contact with the first and second insulating regions at a position higher than the lower end of the first well;
• and
• the second sub-region is in contact with the third and fourth insulating regions at a position higher than the lower end of the second well.