US 2013/0154022 A1 · CMOS Devices with Metal Gates and Methods for Forming the Same

Abstract

A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.

Claims20

Dependent claims

A method comprising:

forming a P-type Metal-Oxide-Semiconductor (PMOS) device comprising:
forming a gate dielectric layer over a semiconductor substrate and in a PMOS region;
forming a first metal-containing layer over the gate dielectric layer and in the PMOS region;
performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas;
and
forming a second metal-containing layer over the first metal-containing layer and in the PMOS region, wherein the second metal-containing layer has a work function lower than a mid-gap work function of silicon, and wherein the first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.

3 more elements

A method comprising:

forming a gate dielectric layer over a semiconductor substrate, wherein the gate dielectric layer comprises a first portion in a P-type Metal-Oxide-Semiconductor (PMOS) region and a second portion in an N-type Metal-Oxide-Semiconductor (NMOS) region;
forming a first metal-containing layer over the gate dielectric layer, wherein the first metal-containing layer comprises a first portion in the PMOS region and a second portion in the NMOS region;
forming a dummy layer over the first metal-containing layer, wherein the dummy layer comprises a first portion in the PMOS region and a second portion in the NMOS region;
removing the first portion of the dummy layer to expose the first portion of the first metal-containing layer;
performing a treatment on the first portion of the first metal-containing layer, wherein during the treatment, the second portion of the first metal-containing layer is covered by at least a lower portion of the second portion of the dummy layer;
removing the at least the lower portion of the second portion of the dummy layer;
and
simultaneously filling a second metal-containing layer into a first opening and a second opening, wherein the first opening is left by the removed first portion of the dummy layer, and the second opening is left by the removed second portion of the dummy layer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/331,214Filed 20 Dec 2011

Published

20 Jun 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 64/01318
Characterised by the conductor: the conductor comprising a layer of alloy material, compound material or organic material contacting the…
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10D 64/667
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: the conductor comprising a layer of…

CMOS Devices with Metal Gates and Methods for Forming the Same

Life of this patent

CMOS Devices with Metal Gates and Methods for Forming the Same

Life of this patent

Abstract

Claims20