System, method and apparatus for seedless electroplated structure on a semiconductor substrate

A method of forming a seedless electroplated metal on a semiconductor surface, comprising:

• providing a silicon substrate;
• forming a mask directly on the silicon substrate without a seed layer, the mask having a thickness of less than 100 nm, and the mask having openings with widths that are less than 100 nm;
• wherein
• the substrate is masked in regions of insulators and regions of silicon, and the silicon regions are isolated from other silicon regions;
• coating the substrate with a polymer that is compatible with a block copolymer (BCP) to allow the BCP to produce a desired mask pattern, the BCP chemically bonds to the substrate at locations of the silicon regions, the polymer having equal chemical affinity to different constituents of the BCP, and the BCP forming the desired mask pattern via phase separation, and the desired mask pattern has part of the BCP removed to expose the substrate;
• removing an oxide on the silicon substrate with buffered oxide etch (BOE) containing a surfactant;
• and
• electroplating a metal through the mask to form electrical connections on the silicon substrate, and the silicon substrate acts as a cathode to form plated electrical connections.

An integrated circuit (IC), comprising:

• a doped silicon semiconductor having regions of insulators and regions of bare silicon, the bare silicon regions are isolated from other bare silicon regions;
• a semiconductor device on the doped silicon semiconductor, the semiconductor device having at least two electrical connections to form regions of patterned metal, said at least two electrical connections comprise at least one of a source, a drain, and a gate connection;
• a metal electroplated directly on each of the regions of patterned metal to form plated connections without a seed layer;
• and
• a self-aligned silicide under each plated connection, formed by annealing, for the regions of plated metal on bare silicon.