Low threshold voltage cmos device

A method of making a semiconductor device comprising:

• providing a substrate having an NMOS region and a PMOS region;
• forming a high-k dielectric layer over the NMOS region and the PMOS region;
• incorporating a metal into the high-k dielectric layer over at least one of the NMOS region and the PMOS region wherein the metal is lanthanum if incorporated into the high-k dielectric over the NMOS region and the metal is aluminum if incorporated into the high-k dielectric over the PMOS region;
• depositing a nitride or carbide layer over the NMOS and PMOS regions;
• depositing a silicon layer over the nitride layer;
• patterning a gate structure of the nitride layer and the silicon layer over the NMOS and PMOS regions;
• applying an interlevel dielectric between the gate structure over the NMOS region and the gate structure over the PMOS region;
• removing the silicon layer from the gate structure over the NMOS region and the gate structure over the PMOS region to leave an opening in the gate structures;
• depositing a first work function setting metal in the opening over the NMOS region and depositing a second work function setting metal in the opening over the PMOS region to partially fill the openings;
• and
• depositing a fill metal to fill the openings.

A method of making a semiconductor device comprising:

• providing a substrate having an NMOS region and a PMOS region;
• forming a gate structure on each of the NMOS region and the PMOS region;
• applying an interlevel dielectric between the gate structure over the NMOS region and the gate structure over the PMOS region;
• removing the gate structure over the NMOS region and the gate structure over the PMOS region to leave an opening in the interlevel dielectric over each of the NMOS region and the PMOS region;
• depositing at least one of:
• lanthanum oxide in the opening over the NMOS region, aluminum oxide in the opening over the PMOS region;
• depositing a high-k dielectric in each of the openings over the NMOS region and the PMOS region;
• depositing a first work function setting metal in the opening over the NMOS region and depositing a second work function setting metal in the opening over the PMOS region to partially fill the openings;
• and
• depositing a fill metal to fill the openings.