Semiconductor device and method of manufacturing the same
AssigneeElpida Memory, Inc.
InventorMika NISHISAKA
Life of this patent
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Abstract
A semiconductor device is provided, which includes a circuit including a first MOS transistor having a gate connected to a first signal line, a second MOS transistor having a gate connected to a second signal line, and the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line, wherein channel regions of the first and second MOS transistors include no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms source and drain regions of the MOS transistors.
Claims23
A semiconductor device comprising:
- first and second MOS transistors, each MOS transistor comprising source and drain regions formed on a main surface of a semiconductor substrate, a channel region sandwiched between the source and drain regions, and a gate electrode provided over the channel region through a gate insulating film;
- and
- a circuit comprising the first MOS transistor whose gate is connected to a first signal line and the second MOS transistor whose gate is connected to a second signal line, the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line,
- wherein the channel regions of the first and second MOS transistors include no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms the source and drain regions.
A semiconductor device comprising:
- a first MOS transistor comprising source and drain regions formed on a main surface of a semiconductor substrate, a channel region sandwiched between the source and drain regions and a gate electrode provided over the channel region through a gate insulating film;
- and
- a circuit comprising the first MOS transistor whose gate electrode receives an input signal having an intermediate potential between a power supply potential and a ground potential, the circuit outputting an output signal according to the potential of the input signal,
- wherein the channel region of the first MOS transistor includes no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms the source and drain regions.
(canceled)
The semiconductor device according to claim 21, wherein a width of the gate electrode of the first and second MOS transistors is larger than a width of the gate electrode of the third MOS transistor.
The semiconductor device according to claim 21, wherein the circuit is a sense amplifier circuit of a DRAM.
The semiconductor device according to claim 21, wherein the circuit is a current mirror differential amplifier circuit.
(canceled)
The semiconductor device according to claim 23, wherein the first impurity comprises indium.
(canceled)
A method of manufacturing a semiconductor device, which comprises first and second MOS transistors, each MOS transistor including source and drain regions formed on a main surface of a semiconductor substrate, a channel region sandwiched between the source and drain regions, and a gate electrode provided over the channel region through a gate insulating film;
- and a circuit comprising the first MOS transistor whose gate is connected to a first signal line and the second MOS transistor whose gate is connected to a second signal line, the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line, the method comprising no step of implanting one conduction type impurity into the channel regions of the first and second MOS transistors so that a concentration of the one conduction type impurity has a maximum value at an area, which is shallower than a depth indicating the maximum concentration of the other conduction type impurity that forms the source and drain regions.
Dependencies are inferred from the claim text.