US 2013/0154004 A1 · SEMICONDUCTOR DEVICE WITH BIASED FEATURE

Abstract

A method of fabricating a semiconductor device includes forming a plurality of line element on a provided substrate. The plurality of line elements includes a first line element having a first region having a first width and a biased region having a second width. The second width different than the first width. Spacer elements are then formed abutting sidewalls of each of the plurality of line elements including the biased region where the spacer elements may be shifted. After forming the spacer elements, the plurality of line elements from the substrate are removed from the substrate. An underlying layer is etched using the spacer elements after removing the plurality of line elements.

Claims20

Dependent claims

A method of fabricating a semiconductor device, comprising:

providing a substrate;
forming a plurality of line elements on the substrate including a first line element having a first region with a first width and a biased region with a second width, the second width different than the first width;
forming spacer elements abutting sidewalls of each of the plurality of line elements;
after forming the spacer elements, removing the plurality of line elements from the substrate;
and
etching an underlying layer using the spacer elements after removing the plurality of line elements.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/399,502Filed 17 Feb 2012

Priority

16 Dec 2011

Published

20 Jun 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10P 76/4085
Characterised by their sizes, orientations, dispositions, behaviours or shapes: characterised by the processes involved to create the masks
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 64/01328
Aspects related to lithography, isolation or planarisation of the conductor: by defining the conductor using a sidewall spacer mask, a…

Semiconductor device with biased feature

Life of this patent

Semiconductor device with biased feature

Life of this patent

Abstract

Claims20