Asymmetric anti-halo field effect transistor

A method of forming an integrated circuit structure, said method comprising:

• implanting a first compensating implant into a substrate;
• patterning a mask on said first compensating implant in said substrate, said mask including an opening exposing a channel location of said substrate;
• implanting a second compensating implant into said channel location of said substrate through said opening at an angle that is offset from perpendicular to a top surface of said substrate, said second compensating implant being positioned closer to a first side of said channel location relative to an opposite second side of said channel location, and said second compensating implant comprising a material having the same doping polarity as said semiconductor channel implant;
• forming a gate conductor above said channel location of said substrate in said opening of said mask;
• removing said mask to leave said gate conductor standing on said channel location of said substrate;
• implanting source and drain extensions into source/drain regions of said substrate adjacent to said channel location using said gate conductor as an alignment device;
• forming sidewall spacers on said gate conductor;
• and
• implanting source and drain implants into said source/drain regions of said substrate using said sidewall spacers as an alignment device.

A method of forming an integrated circuit structure, said method comprising:

• implanting a first compensating implant into a substrate;
• after implanting said first compensating implant, patterning a mask on said first compensating implant in said substrate, said mask including an opening exposing a channel location of said substrate;
• after patterning said mask, forming a gate insulator material on said mask and said channel location of said substrate;
• after patterning said mask, implanting a second compensating implant into said channel location of said substrate through said opening at an angle that is offset from perpendicular to a top surface of said substrate, said second compensating implant being positioned closer to a first side of said channel location relative to an opposite second side of said channel location, and said second compensating implant comprising a material having the same doping polarity as said semiconductor channel implant;
• after implanting said second compensating implant, forming a gate conductor on said channel location of said substrate in said opening of said mask;
• after forming said gate conductor, removing said mask to leave said gate conductor standing on said channel location of said substrate, a size of said opening in said mask controls a size of said second compensating implant within said channel location of said substrate, without affecting a size of said first compensating implant within said channel location of said substrate;
• after removing said mask, implanting source and drain extensions into source/drain regions of said substrate adjacent to said channel location using said gate conductor as an alignment device;
• after removing said mask, forming sidewall spacers on said gate conductor;
• and
• after forming said sidewall spacers, implanting source and drain implants into said source/drain regions of said substrate using said sidewall spacers as an alignment device.

An integrated circuit structure comprising:

• a semiconductor channel implant extending into a substrate to a first depth;
• a first compensating implant extending into said substrate to a second depth, said first depth being further from a top surface of said substrate relative to said second depth, said first compensating implant comprising a material having a different doping polarity than said semiconductor channel implant;
• a gate insulator material on a channel location of said substrate;
• a second compensating implant in said channel location of said substrate, said second compensating implant being positioned closer to a first side of said channel location relative to an opposite second side of said channel location, and said second compensating implant comprising a material having the same doping polarity as said semiconductor channel implant;
• a gate conductor on said gate insulator material over said channel location of said substrate;
• source and drain extensions in source/drain regions of said substrate adjacent to said channel location;
• sidewall spacers on said gate conductor;
• and
• source and drain implants in said source/drain regions of said substrate.