FinFETs with Multiple Threshold Voltages
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chin Kuo, Hsien-Ming Lee
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Abstract
A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.
Claims20
A device comprising:
- a substrate;
- a semiconductor fin over the substrate;
- a gate dielectric layer on a top surface and sidewalls of the semiconductor fin;
- and
- a gate electrode spaced apart from the semiconductor fin by the gate dielectric layer, wherein the gate electrode comprises a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer, and wherein the top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.
A device comprising:
- a substrate;
- a semiconductor fin over the substrate, wherein the semiconductor fin is a part of a Fin Field-Effect Transistor (FinFET);
- a gate dielectric layer on a top surface and sidewalls of the semiconductor fin;
- and
- a gate electrode spaced apart from the semiconductor fin by the gate dielectric layer, wherein the gate electrode comprises:
- a first metal layer over and aligned to the semiconductor fin, wherein the first metal layer does not comprise substantial portions that are lower than a top surface of the semiconductor fin;
- and
- a second metal layer comprising a first portion over and aligned to the first metal layer, and second portions lower than the top surface of the semiconductor fin, wherein the first metal layer and the second metal layer comprise different materials, and wherein the first metal layer and the first portion of the second metal layer form a top portion of a gate electrode of the FinFET, and the second portions of the second metal layer form sidewall portions of the gate electrode of the FinFET.
A method comprising:
- forming a gate dielectric on a semiconductor fin, wherein the gate dielectric comprises a top portion over a top surface of the semiconductor fin, and sidewall portions on sidewalls of the semiconductor fin;
- forming a first metal layer over the top portion of the gate dielectric, wherein the first metal layer does not comprise portions extending on the sidewall portions of the gate dielectric;
- and
- forming a second metal layer, wherein the second metal layer comprises a first portion over the first metal layer, and second portions extending on the sidewall portions of the gate dielectric, and wherein the first and the second metal layers comprise different materials.
Dependencies are inferred from the claim text.