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US 2013/0153996 A1Published application
Hybrid cmos nanowire mesh device and pdsoi device
AssigneeInternational Business Machines Corporation
InventorsJosephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
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Abstract
A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.
Claims20
A method of forming a hybrid semiconductor structure comprising:
- providing a semiconductor on insulator substrate comprising a top semiconductor layer and a buried insulating layer;
- providing a material stack on top of the top semiconductor layer, the material stack including alternating layers of semiconductor material and sacrificial material, wherein the bottommost layer of the patterned material stack is the top semiconductor layer of the semiconductor on insulator substrate;
- providing a hard mask over the patterned material stack;
- blocking the hard mask and material stack in a first portion of the semiconductor structure;
- removing the hard mask and material stack in a second portion of the semiconductor structure while leaving a layer of the top semiconductor layer;
- regrowing the layer of the top semiconductor layer into a thicker layer of the top semiconductor layer in the second portion of the semiconductor structure to form a partially depleted semiconductor on insulator (PDSOI) layer;
- patterning the hard mask to form a plurality of hard mask structures in the first portion of the semiconductor structure;
- forming a dummy gate over a central portion of each of said plurality of hard mask structures in the first portion of the semiconductor structure and over a central portion of the PDSOI layer in the second portion of the semiconductor structure;
- forming a sacrificial material layer abutting the dummy gates in the first and second portions of the semiconductor structure;
- removing the dummy gates to form a trench in the sacrificial material layer of each of the first and second portions of the semiconductor structure to expose the central portion of each of said plurality of hard mask structures in the first portion of the semiconductor structure and the central portion of the PDSOI layer in the second portion of the semiconductor structure;
- blocking the second portion of the semiconductor structure;
- etching a plurality of fins within the trench in the patterned material stack in the first portion of the semiconductor structure using the plurality of patterned hard masks as an etch mask;
- removing the plurality of patterned hard masks in the first portion of the semiconductor structure;
- removing each layer of sacrificial material within the trench in the first portion of the semiconductor structure to form a plurality of vertically stacked and vertically spaced apart semiconductor nanowires within the trench in the first portion of the semiconductor structure;
- and
- filling the trenches in the first and second portions of the semiconductor structure with a gate region.
13 more elements
A semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate comprising:
- a first portion of the SOI substrate containing at least one nanowire mesh device and a second portion of the SOI substrate containing at least one partially depleted semiconductor on insulator (PDSOI) device;
- the at least one nanowire mesh device comprising:
- a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;
- and a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region;
- the at least one PDSOI device comprising:
- a partially depleted semiconductor layer on the substrate;
- and a gate region including a gate dielectric and a gate conductor over at least a portion of the partially depleted semiconductor layer.
4 more elements
An integrated circuit comprising:
- an semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate, the semiconductor hybrid structure comprising:
- first portions of the SOI substrate containing a plurality of nanowire mesh devices and second portions of the SOI substrate containing a plurality of partially depleted semiconductor on insulator (PDSOI) devices;
- each of the plurality of nanowire mesh devices comprising:
- a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;
- and a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region;
- each of the plurality of PDSOI devices comprising:
- a partially depleted semiconductor layer on the substrate;
- and a gate region including a gate dielectric and a gate conductor over at least a portion of the partially depleted semiconductor layer.
5 more elements
Dependencies are inferred from the claim text.