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US 2013/0153960 A1Published application
Anti-Fuses on Semiconductor Fins
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHsiao-Lan Yang
Life of this patent
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Abstract
A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
Claims20
A device comprising:
- a substrate;
- isolation regions at a surface of the substrate;
- a semiconductor region over a top surface of the isolation regions;
- a conductive feature over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region;
- and
- a dielectric material between the conductive feature and the semiconductor region, wherein the dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
3 more elements
A device comprising:
- a semiconductor substrate;
- Shallow Trench Isolation (STI) regions at a surface of the semiconductor substrate;
- a first semiconductor fin over top surfaces of the STI regions;
- a second semiconductor fin over the top surfaces of the STI regions, wherein the first and the second semiconductor fins comprise facets;
- and
- a dielectric material between the first and the second semiconductor fins, wherein the dielectric material, the first semiconductor fin, and the second semiconductor fin form an anti-fuse.
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A method comprising:
- performing an epitaxy to form an epitaxy region over a top surface of a Shallow Trench Isolation (STI) region, wherein the STI region is at a surface of a substrate;
- forming a silicide region over and contacting the epitaxy region;
- forming a conductive region adjacent to the silicide region and over the STI region;
- filling a dielectric material between the conductive region and a combined region of the silicide region and the epitaxy region, wherein the conductive region, the combined region, and the dielectric material form an anti-fuse;
- and
- forming a power source electrically couple to the silicide region and the conductive region, wherein the power source is configured to apply a programming voltage high enough to program the anti-fuse.
3 more elements
Dependencies are inferred from the claim text.