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US 2013/0153896 A1Published application
SCAN TESTABLE THROUGH SILICON VIAs
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.
Claims24
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV having a top end and bottom end,
- a scan cell having a response input and a stimulus output,
- a first switch selectively coupling the top end of the TSV to one of the top surface contact point and the response input to the scan cell,
- a second switch selectively coupling the bottom end of the TSV to one of the bottom surface contact point and the stimulus output of the scan cell, and;
- a first control signal for controlling the first switch and a second control signal for controlling the second switch.
5 more elements
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV having a top end and bottom end,
- a scan cell having a response input and a stimulus output,
- a connection formed between the top end of the TSV, the top surface contact point and the response input to the scan cell,
- a switch selectively coupling the bottom end of the TSV to one of the bottom surface contact point and the stimulus output of the scan cell, and;
- a control signal for controlling the switch.
5 more elements
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV having a top end and bottom end,
- a scan cell having a response input and a stimulus output,
- a connection formed between the top end of the TSV, the top surface contact point and the response input to the scan cell,
- a 3-state buffer having an input connected to the bottom surface contact point, a control input and an output connected to the bottom end of the TSV and the stimulus output of the scan cell, and;
- a control signal for controlling the control input of the 3-state buffer.
5 more elements
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV having a top end and bottom end,
- a scan cell having a response input and a stimulus output,
- a connection formed between the bottom end of the TSV, the bottom surface contact point and the response input to the scan cell,
- a 3-state buffer having an input connected to the top surface contact point, a control input and an output connected to the top end of the TSV and the stimulus output of the scan cell, and;
- a control signal for controlling the control input of the 3-state buffer.
5 more elements
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV having a top end and bottom end,
- a scan cell having a response input and a stimulus output,
- a 3-state buffer having an input connected to the bottom surface contact point, a control input and an output connected to the bottom end of the TSV and the stimulus output of the scan cell,
- a buffer having an input connected to the top end of the TSV and the response input to the scan cell and an output connected to the top surface contact point, and;
- a control signal for controlling the control input of the 3-state buffer.
5 more elements
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV having a top end and bottom end,
- a scan cell having a response input and a stimulus output,
- a 3-state buffer having an input connected to the top surface contact point, a control input and an output connected to the top end of the TSV and the stimulus output of the scan cell,
- a buffer having an input connected to the bottom end of the TSV and the response input to the scan cell and an output connected to the bottom surface contact point, and;
- a control signal for controlling the control input of the 3-state buffer.
5 more elements
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV having a top end and bottom end,
- a scan cell having a response input and a stimulus output,
- a 3-state buffer having an input connected to the bottom surface contact point, a control input and an output connected to the bottom end of the TSV and the stimulus output of the scan cell,
- a buffer having an input connected to the top end of the TSV and an output connected to the top surface contact point,
- a switch having a first terminal connected to the buffer input, a second terminal connected to the buffer output, a third terminal connected to the response input of the scan cell and a control input, and;
- a control signal for controlling the control input of the 3-state buffer and a control signal for controlling the control input of the switch.
6 more elements
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV having a top end and bottom end,
- a scan cell having a response input and a stimulus output,
- a 3-state buffer having an input connected to the top surface contact point, a control input and an output connected to the top end of the TSV and the stimulus output of the scan cell,
- a buffer having an input connected to the bottom end of the TSV and an output connected to the bottom surface contact point,
- a switch having a first terminal connected to the buffer input, a second terminal connected to the buffer output, a third terminal connected to the response input of the scan cell and a control input, and;
- a control signal for controlling the control input of the 3-state buffer and a control signal for controlling the control input of the switch.
6 more elements
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV coupled between the top surface contact point and bottom surface contact point,
- test circuitry associated with the TSV,
- a functional output circuit coupled to the TSV via a 3-state buffer which is part of the test circuitry, and;
- a test mode signal connected to the control input of the 3-state buffer for disabling the 3-state buffer when the TSV is being tested by the test circuitry.
4 more elements
An integrated circuit die including;
- a top surface and a bottom surface,
- a contact point on the top surface,
- a contact point on the bottom surface,
- a TSV coupled between the top surface contact point and bottom surface contact point, test circuitry associated with the TSV,
- a functional output circuit coupled to the TSV via a functional 3-state buffer,
- a control output from the functional output circuit for controlling the functional 3-state buffer to one of an enabled and disabled state,
- a gate having an first input connected to the control output of the output circuit, an output connected to a control input of the functional 3-state buffer and a second input, and:
- a test mode signal connected to the second input for disabling the functional 3-state buffer when the TSV is being tested by the test circuitry.
5 more elements
A scan cell within an integrated circuit including;
- a test response (R) input terminal, a voltage reference (VR) input terminal, a serial data input (SI) terminal, a capture/shift (CS) input terminal, a scan clock (SC) input terminal, an output enable (OE) input terminal, a serial data output (SO) terminal, a test stimulus (S) output terminal, a voltage (V) level terminal and a ground (G) level terminal.
- a comparator having an input coupled to the test response input terminal, an input coupled to the voltage reference input terminal and an output,
- a multiplexer having an input coupled to the output of the comparator, an input coupled to the serial data input terminal, an input coupled to the capture/shift input terminal and an output,
- a memory having an input coupled to the output of the multiplexer, an input coupled to the scan clock input terminal and an output coupled to the serial data output terminal, and;
- a stimulus output circuit having an input coupled to the output of the memory, an input coupled to the output enable input terminal, a connection to the voltage level terminal, a connection to the ground level terminal and an output coupled to the test stimulus output terminal.
2 more elements
An integrated circuit including;
- a voltage reference contact point, a serial input contact point, control bus contact points, a serial output contact point,
- a voltage selection circuit having an output for providing a selectable voltage level and a voltage selection control input from the control bus, and;
- scan cells connected serially between the serial input and serial output contact points, each scan cell having control inputs connected to control signals of the control bus contact points and a voltage level lead connected to the voltage level output of the voltage selection circuit.
An integrated circuit including;
- a bottom surface including a voltage reference contact point, a serial input contact point, control bus contact points, up control contact points, and a serial output contact point,
- a top surface including a voltage reference contact point, a serial output contact point, control bus contact points, up control contact points, and a serial input contact point,
- a voltage selection circuit having an output for providing a selectable voltage level and a voltage selection control input from the control bus contact points of the bottom surface,
- a group of serially connected scan cells, the group having a data input connected to the bottoms surface serial input terminal, control inputs connected to some of the bottom surface control bus contact points and a data output, and;
- a multiplexer having an input connected to the data output of the group of serial connected scan cells, an input connected to the serial input contact point of the top surface and an output connected to the serial output contact point on the bottom surface.
2 more elements
An integrated circuit including;
- a voltage reference contact point and TDI, TCK, TMS and TDO contact points,
- a TAP connected to the TDI, TCK, TMS and TDO contact points and having TDI output lead, a TDO input lead and control bus output leads,
- a voltage selection circuit having an output for providing a selectable voltage level and a voltage selection control input from the control bus output leads, and;
- scan cells connected serially between the TAP TDI output lead and TDO input lead, each scan cell having control inputs connected to control signals of the control bus output leads and a voltage level lead connected to the voltage level output of the voltage selection circuit.
1 more element
An integrated circuit including;
- a bottom surface including a voltage reference contact point and TDI, TCK, TMS and TDO contact points,
- a top surface including a voltage reference terminal and TDI, TCK, TMS, and TDO contact points,
- a TAP connected to the TDI, TCK, TMS and TDO contact points of the bottom surface and having first and second TDI output leads, first and second TDO input leads and control bus output leads,
- a voltage selection circuit having an output for providing a selectable voltage level and a voltage selection control input from the control output bus of the TAP,
- a group of serially connected scan cells, the group having a data input connected to the first TDI output lead, control inputs connected to some of the control bus output leads, and a data output connected to the first TDO input lead,
- a connection formed between the second TDI output lead and the TDI contact point on the top surface,
- a connection formed between the TDO contact point on the top surface and the second TDO input lead, and;
- gating circuitry selectively coupling at least one of the TCK and TMS contact points of the bottom surface to a respective one of the TCK and TMS contact points of the top surface.
5 more elements
Dependencies are inferred from the claim text.