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US 2013/0153851 A1Published application
Stack type semiconductor memory device
AssigneeSK hynix Inc.
InventorNam Kyun PARK
Life of this patent
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Abstract
A stack type memory device includes a semiconductor substrate; a plurality of bit lines arranged and stacked on the semiconductor substrate; a plurality of word lines formed on the plurality of bit lines; a plurality of interconnection units, each extending from a respective word line toward a respective one of the plurality of bit lines; and a plurality of memory cells connected between the plurality of bit lines and the interconnection units extending from the plurality of word lines, respectively.
Claims16
A stack type memory device, comprising:
- a semiconductor substrate;
- a plurality of bit lines arranged and stacked on the semiconductor substrate;
- a plurality of word lines formed on the plurality of bit lines;
- a plurality of interconnection units, each extending from a respective word line toward a respective one of the plurality of bit lines;
- and
- a plurality of memory cells connected between the plurality of bit lines and the interconnection units extending from the plurality of word lines, respectively.
3 more elements
A stack type memory device, comprising:
- a semiconductor substrate;
- a plurality of active regions that each include a plurality of active layers that are stacked on the semiconductor substrate and insulated from one another;
- a plurality of gate electrodes that are formed in each of the plurality of active regions and the plurality of gate electrodes surround an upper portion of an uppermost active layer of the plurality of active layers and side portions of the plurality of active layers;
- a plurality of sources that are each formed in each of the plurality of active layers at a first side of the gate electrode;
- a plurality drains that are each formed in each of the plurality of active layers at a second side of the gate electrode;
- a plurality of bit lines that are each commonly connected to drains disposed in the same layer;
- a plurality of resistive device layers that are each connected to a respective one of the plurality of sources;
- and
- a common source line commonly connected to the resistive device layers.
6 more elements
A stack type memory device, comprising:
- a semiconductor substrate;
- a plurality of active regions that each include a plurality of active layers that are stacked on the semiconductor substrate and insulated from one another;
- a plurality of gate electrodes that are formed in each of the plurality of active regions and the plurality of gate electrodes surround an upper portion of an uppermost active layer of the plurality of active layers and side portions of the plurality of active layers;
- a plurality of sources that are each formed in each of the plurality of active layers at a first side of the gate electrode;
- a plurality drains that are each formed in each of the plurality of active layers at a second side of the gate electrode;
- a plurality of resistive device layers that are each arranged at a first side of a respective one of the plurality of the drains;
- a plurality of bit lines that are each commonly connected to resistive device layers arranged in the same layer;
- a common source line commonly connected to the plurality of sources;
- and
- word lines that are each electrically connected to a respective one of the plurality of gate electrodes.
7 more elements
Dependencies are inferred from the claim text.