Back to results
US 2013/0153848 A1Published application
Semiconductor memory device and method of manufacturing the same
OwnerNam Kyun PARK, Kang Sik CHOIinventors
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer.
Claims36
A method of manufacturing a semiconductor memory device, comprising:
- forming a gate cell material layer on a bit line;
- etching a portion of the gate cell material layer in a line shape in a direction that the bit line extends to form a line shape etched region;
- forming a first spacer insulating layer in the line shape etched region;
- performing an etch-back process on the first spacer insulating layer to expose the bit line and form an etch-back region;
- forming a first oxide layer below the first spacer insulating layer;
- forming a first buried insulating layer in the etch-back region;
- etching the gate cell material layer in a direction perpendicular to the direction that the bit line extends to form a first trench;
- forming a second spacer insulating layer in the first trench on sidewalls of the gate cell material layer;
- performing an etch-back process on the second spacer insulating layer to expose the bit line;
- forming a second oxide layer below the second spacer insulating layer;
- forming a second buried insulating layer in the first trench;
- removing the first spacer insulating layer and the second spacer insulating layer;
- sequentially forming a gate oxide layer and a gate metal layer in a space formed by removing the first and second spacer insulating layer;
- removing a portion of the gate oxide layer and the gate metal layer;
- forming a third buried insulating layer in a space formed by removing the portion of the gate oxide layer and the gate metal layer;
- removing an upper portion of the gate cell material layer;
- sequentially forming a lower electrode and a data storage material layer in a space formed by removing the upper portion of the gate cell material layer;
- and
- forming an interconnection layer on the data storage material layer.
16 more elements
A method of manufacturing a semiconductor memory device, comprising:
- forming a gate cell material layer on a bit line;
- etching a portion of the gate cell material layer in a direction perpendicular to a direction that the bit line extends to form a first trench;
- forming a spacer insulating layer in the first trench on sidewalls of the gate cell material layer;
- forming an oxide layer below the space insulating layer;
- forming a first buried insulating layer in the first trench;
- removing the spacer insulating layer;
- sequentially forming a gate oxide layer and a gate metal layer in a space formed by removing the spacer insulating layer;
- removing a portion of the gate oxide layer and the gate metal layer;
- forming a second buried insulating layer in a space formed by removing the portion of the gate oxide layer and the gate metal layer;
- removing an upper portion of the gate cell material layer;
- sequentially forming a lower electrode and a data storage material layer a space formed by removing the upper portion of the gate cell material layer;
- and
- forming an interconnection layer on the data storage material layer.
10 more elements
A method of manufacturing a semiconductor memory device, comprising:
- forming a gate cell material layer on a bit line;
- patterning the gate cell material layer in a pillar shape;
- forming an insulating layer in a bottom portion of a region where the gate cell material layer is removed;
- forming a gate oxide layer on an exposed sidewall of the gate cell material layer;
- forming a gate metal layer on the gate oxide layer in the region where the gate cell material layer is removed;
- forming a first buried insulating layer in the region where the gate cell material layer is removed;
- removing a portion of the gate oxide layer and the gate metal layer;
- forming a second buried insulating layer in a space formed by removing the gate oxide layer and the gate metal layer;
- removing an upper portion of the gate cell material layer;
- sequentially forming a lower electrode and a data storage material layer in a space formed by removing the upper portion of the gate cell material layer;
- and
- forming an interconnection layer on the data storage material layer.
9 more elements
The method of claim 31, further comprising forming a multi-stack structure including at least one cell having the same structure as a cell formed below the interconnection layer.
A semiconductor memory device, comprising:
- a bit line extending in a first direction;
- a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape;
- a lower electrode and a data storage material layer formed on the vertical gate cell;
- and
- an interconnection layer formed on the data storage material layer.
2 more elements
A semiconductor memory device, comprising:
- a bit line;
- a cell structure having a pattern shape formed on the bit line;
- and
- a vertical gate structure formed on a sidewall of the cell structure.
1 more element
A semiconductor memory device, comprising:
- a first bit line;
- a first cell structure formed on the first bit line, wherein a gate electrode structure of the first cell structure is formed on an outer circumference of the first cell structure;
- a first data storage material layer formed on the first cell structure;
- a common source line formed on the first data storage material layer;
- a second cell structure formed on the common source line, wherein a gate electrode structure of the second cell structure is formed on an outer circumference of the second cell structure;
- a second data storage material layer formed on the second cell structure;
- and
- a second bit line formed on the second data storage material layer.
5 more elements
Dependencies are inferred from the claim text.