Scan frame based test access mechanisms

An integrated circuit comprising;

• A. core circuitry having scan paths, the scan paths including scan data input leads, scan data output leads, and scan control input leads;
• and
• B. a test access mechanism having:
• i. a serial data input lead,
• ii. a serial data output lead,
• iii. parallel data output leads coupled to the to the scan data input leads,
• iv. parallel data input leads coupled to the scan data output leads,
• v. control output leads coupled to the scan control input leads,
• vi. a clock signal input;
• vii. a functional clock signal input;
• viii. a test/read input,
• ix. a test access mechanism enable input, and
• x. a scan frame input register having an input coupled with the serial data input lead, the scan frame input lead including in series from the input coupled with the serial data input lead a stimulus section, a command section, and a frame marker section.