Integrated circuit method with triple patterning
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Chu Liu, Kuei Shun Chen, Meng Wei Chen
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Abstract
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.
Claims22
An integrated circuit (IC) design method comprising:
- receiving an IC design layout having a plurality of IC features;
- identifying, from the IC design layout,
- simple features as a first layout wherein the first layout does not violate design rules, and
- complex features as a second layout wherein the second layout violates the design rules;
- and
- generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.
A method for making an integrated circuit (IC), comprising:
- forming a material layer on a substrate;
- patterning a first photoresist layer on the material layer using a first photomask;
- etching the material layer through openings of the first photoresist layer;
- removing the first photoresist layer;
- patterning a second photoresist layer on the material layer using a second photomask and a third photomask;
- etching the material layer through openings of the second photoresist layer;
- and
- removing the second photoresist layer.
A set of photomasks designed to form integrated circuit (IC) features in a material layer, comprising:
- a first photomask that includes a first layout having a first subset of the IC features, wherein the first layout does not violate design rules;
- a second photomask that includes a second layout having a second subset of the IC features and connecting features, wherein the second subset of the IC features violate the design rules and the second layout does not violate the design rules;
- and
- a third photomask that includes a third layout having a plurality of trimming features that match the connecting features.
Dependencies are inferred from the claim text.