Performance and reducing variation of narrow channel devices

A method of forming a transistor, comprising:

• forming a gate stack on top of a transistor region of a substrate, said transistor region of said substrate including a channel region, a source region, and a drain region, said channel region being underneath said gate stack, said source region being between said channel region and a first shallow trench insulation (STI) region, and said drain region being between said channel region and a second STI region, and said first and second STI regions having a height higher than said region of said substrate;
• forming spacers at sidewalls of said first and second STI regions above said substrate;
• creating recesses in said source region and said drain region, with said spacers preserving at least a portion of said substrate along sidewalls of said first and second STI regions underneath said spacers;
• epitaxially growing source and drain of said transistor in said recesses.

A method comprising:

• creating a plurality of transistor regions of a substrate, said transistor regions being separated by one or more shallow trench isolation (STI) regions formed in said substrate and including a channel region, a source region, and a drain region, wherein said one or more STI regions have a height higher than a top surface of said substrate;
• forming a gate stack on top of said channel region;
• depositing a conformal dielectric layer on top of said gate stack, said source and drain regions of said substrate, and said one or more STI regions;
• directionally etching said conformal dielectric layer into spacers at sidewalls, at above said surface of said substrate, of said one or more STI regions;
• creating recesses in said source region and said drain region with said spacers preserving at least a portion of material of said substrate along sidewalls at below said surface of said substrate, of said one or more STI regions;
• and
• epitaxially growing source and drain of said transistor in said recesses.