Collision prevention in a dual port memory

A register file memory comprising:

• a memory array including a plurality of dual port bit cells arranged in rows and columns, wherein each bit cell is configured to store a data bit;
• and
• a wordline unit coupled to the memory array and configured to provide a respective write wordline signal and a respective read wordline signal to each row of bit cells, wherein the wordline unit is further configured to selectively inhibit the read wordline signal for a given row in response to determining that a write operation will be performed to the given row;
• wherein the wordline unit includes detection logic configured to selectively generate a read wordline mask signal to inhibit the read wordline signal dependent upon whether the one or more bits of a partially decoded write address correspond to the given row.

A system comprising:

• a memory;
• and
• one or more processors coupled to the memory, wherein at least one of the one or more processors includes a register file memory;
• wherein the register file memory includes:
• a plurality of dual port bit cells arranged in rows and columns, wherein each bit cell is configured to store a data bit;
• and
• a wordline unit configured to provide a respective write wordline signal and a respective read wordline signal to each row of bit cells, wherein the wordline unit is further configured to selectively inhibit the read wordline signal for a given row based upon one or more bits of a partially decoded write address that indicate whether a write operation will be performed to the given row;
• wherein the wordline unit includes detection logic configured to selectively generate a read wordline mask signal to inhibit the read wordline signal dependent upon whether the one or more bits of the partially decoded write address correspond to the given row.

A method comprising:

• receiving a respective write wordline signal and a respective read wordline signal at each row of bit cells of a plurality of bit cells arranged into rows and columns of a memory array;
• and
• a wordline unit selectively inhibiting the respective read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row;
• wherein the selectively inhibiting includes detecting a write operation to the given row and inhibiting the read wordline signal to the given row;
• wherein detecting the write operation to the given row includes performing a logic operation between a first partially decoded write address bit and a second partially decoded write address bit to selectively generate a read wordline mask signal for selectively inhibiting the read wordline signal.

A mobile communication device comprising:

• a memory,
• a processor coupled to the memory, wherein the processor includes a register file memory including:
• a plurality of dual port bit cells arranged in rows and columns, wherein each bit cell is configured to store a data bit;
• a wordline unit configured to provide a respective write wordline signal and a respective read wordline signal to each row of bit cells, wherein the wordline unit is further configured to selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row;
• wherein the wordline unit includes detection logic configured to selectively generate a read wordline mask signal to inhibit the read wordline signal dependent upon whether one or more bits of a partially decoded write address correspond to the given row.