Interfaces and die packages, and appartuses including the same

An interface, comprising:

• a control input buffer configured to receive an enable signal;
• a first input buffer configured to receive a first data and provide a first input data;
• a second input buffer configured to receive a second data and provide a second input data;
• and
• an input multiplexer configured to multiplex the first input data and the second input data to provide integrated data in response to the enable signal.

A memory device, comprising:

• a plurality of memory dies;
• an interface comprising:
• a control input buffer configured to receive an enable signal through a control pad from a first group of the plurality of memory dies, each of the first group of memory dies being coupled to the control pad;
• a first input buffer configured to receive a first data through a first IO pad from the first group of memory dies, each of the first group of memory dies being coupled to the first IO pad;
• a second input buffer configured to receive a second data through a second IO pad from a second group of the plurality of memory dies, each of the second group of memory dies being coupled to the second IO pad;
• and
• an input multiplexer configured to multiplex the first data and the second data to provide integrated data in response to the enable signal.

An interface, comprising:

• an output multiplexer configured to divide output data to provide a first data and a second data in response to an external control signal, the output multiplexer being further configured to provide a first control signal and a second control signal;
• a first pre-driving circuit configured to provide a first pull-up signal and a first pull-down signal in response to the first data and the first control signal;
• a first output buffer configured to provide a first output data in response to the first pull-up signal and the first pull-down signal;
• a second pre-driving circuit configured to provide a second pull-up signal and a second pull-down signal in response to the second data and the second control signal;
• and
• a second output buffer configured to provide a second output data in response to the second pull-up signal and the second pull-down signal.

A memory device, comprising:

• a plurality of memory dies;
• an interface comprising:
• an output multiplexer configured to divide the output data to provide a first data and a second data in response to an external control signal, the output multiplexer being further configured to provide a first control signal and a second control signal;
• a first pre-driving circuit configured to provide a first pull-up signal and a first pull-down signal in response to the first data and the first control signal;
• a first output buffer configured to provide a first output data in response to the first pull-up signal and the first pull-down signal through a first IO pad coupled to a first group of the plurality of memory dies;
• a second pre-driving circuit configured to provide a second pull-up signal and a second pull-down signal in response to the second data and the second control signal;
• and
• a second output buffer configured to provide a second output data in response to the second pull-up signal and the second pull-down signal through a second IO pad coupled to a second group of the plurality of memory dies.