Resistive memory apparatus, layout structure, and sensing circuit thereof

A resistive memory apparatus comprising:

• a first memory area comprising a first main memory cell array coupled between a plurality of first source lines/bit lines and a plurality of first word lines and a first reference cell array coupled between the plurality of first source lines/bit lines and a plurality of first reference word lines;
• a second memory area comprising a second main memory cell array coupled between a plurality of second source lines/bit lines and a plurality of second word lines and a second reference cell array coupled between the plurality of second source lines/bit lines and a plurality of second reference word lines;
• a row address decoder configured to drive a word line or reference word line in response to an external address;
• a column address decoder configured to drive a bit line and a source line in response to an external address;
• and
• a bit line driver/sinker commonly coupled to the first and second memory areas and configured to apply a predetermined voltage to the bit line driven by the column address decoder.

A sensing circuit for a resistive memory apparatus which includes a plurality of memory areas each including a main memory cell array and a reference cell array coupled to a plurality of reference word lines and a bit line driver/sinker shared by adjacent memory areas, the sensing circuit comprising:

• a first sink unit configured to couple a source line coupled to a reference cell of an adjacent memory area sharing the bit line driver/sinker with a selected word line to a ground terminal, in response to a read enable signal;
• a second sink unit configured to couple a source line coupled to a main memory cell of the selected memory area to a ground terminal in response to the read enable signal;
• a sensing unit coupled to a bit line coupled to the reference cell of the adjacent memory area and a bit line coupled to the main memory cell of the selected memory area and configured to sense data of the main memory cell of the selected memory area and output the sensed data to a pre-output terminal;
• and
• a comparison unit configured to compare a reference voltage with a voltage of the pre-output terminal and output read data.

A layout structure of a resistive memory apparatus, comprising:

• a plurality of memory area;
• and
• a bit line driver/sinker arranged between adjacent memory areas,
• wherein each of the memory areas comprises:
• a plurality of bit lines/source lines;
• a plurality of word lines configured to cross the bit lines/source lines;
• a plurality of reference word lines configured to cross the bit lines/source lines;
• a main memory cell array coupled between the plurality of bit lines/source lines and the plurality of word lines;
• and
• a reference cell array coupled between the plurality of bit lines/source lines and the plurality of reference word lines.