Power-saving receiver circuits, systems and processes
AssigneeTexas Instruments Incorporated
InventorsDeric Wayne Waters, Karthik Ramasubramanian, Arun Raghupathy
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Abstract
An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (TON, TOFF) on the receiver circuit (BSP) inside the coherent summations time interval. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.
Claims21
A power management circuit for controlling a process having a maximum available interval for coherent summations, the power management circuit comprising
- a power gating circuit operable to turn power on and off to at least one portion of the process;
- and
- a control circuit operable to establish a rate of turning the power on and off by said power gating circuit so that the rate equals or exceeds the reciprocal of the maximum available interval for coherent summations.
Dependencies are inferred from the claim text.