US 2013/0093486 A1 · INTEGRATED CIRCUIT HAVING LATCH-UP RECOVERY CIRCUIT

Abstract

An integrated circuit includes first and second transistors, a switch, and a power-on reset (POR) circuit. The first transistor has a first current electrode, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode. The switch is for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal. The POR circuit has a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch. The latch-up detection circuit is for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.

Claims20

Dependent claims

An integrated circuit comprising:

a first transistor having a first current electrode, a second current electrode, and a control electrode;
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode;
a switch for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal;
and
a power-on reset circuit having a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch, the latch-up detection circuit for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.

2 more elements

An integrated circuit comprising:

a first power supply voltage terminal;
a second power supply voltage terminal;
a first P-channel transistor having a first current electrode coupled to the first power supply voltage terminal, a second current electrode, and a control electrode;
a first N-channel transistor having a first current electrode coupled to the second current electrode of the first P-channel transistor, a second current electrode, and a control electrode;
a second N-channel transistor having a first current electrode coupled to the second current electrode of the first N-channel transistor, a second current electrode coupled to the second power supply voltage terminal, and a control electrode;
a first bias control circuit coupled to provide a first bias signal to the control electrode of the second N-channel transistor;
a latch-up detection circuit coupled to the first power supply voltage terminal for detecting when a power supply voltage provided to the first power supply voltage terminal drops below a predetermined threshold voltage;
and
a power-on reset circuit coupled to the latch-up detection circuit and to an input terminal of the bias control circuit, the power-on reset circuit for causing the integrated circuit to initiate a power-on reset sequence and to cause the bias control circuit to make the second N-channel transistor substantially non-conductive.

6 more elements

Dependencies are inferred from the claim text.

Integrated circuit having latch-up recovery circuit

Life of this patent

Integrated circuit having latch-up recovery circuit

Life of this patent

Abstract

Claims20