US 2013/0093482 A1 · CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES

Abstract

An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

Claims7

Dependent claims

1-12. (canceled)

Dependencies are inferred from the claim text.

Facts

Application

13/693,363Filed 4 Dec 2012

Priority

4 Feb 2010

Published

18 Apr 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03L 7/08
Using a reference signal applied to a frequency- or phase-locked loop: details of the phase-locked loop
H03L 7/0807
Details of the phase-locked loop: concerning mainly a recovery circuit for the reference signal
H03L 7/0814
And where no voltage or current controlled oscillator is used: the phase shifting device being digitally controlled
H03L 7/087
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using at least two…

Clock and data recovery circuitry with auto-speed negotiation and other possible features

Life of this patent

Clock and data recovery circuitry with auto-speed negotiation and other possible features

Life of this patent

Abstract

Claims7