Frequency synthesizer and associated method
AssigneeMediatek Inc.
InventorsAng-Sheng Lin, Robert Bogdan Staszewski, Yi-Hsien Cho
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Abstract
A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.
Claims27
A frequency synthesizer comprising:
- a frequency reference input for receiving a frequency reference clock;
- a tuned oscillator for providing an RF clock;
- a phase shifter coupled to said tuned oscillator and arranged to change phase of said RF clock;
- and
- a time-to-digital converter (TDC) coupled to said frequency reference input and said phase shifter, wherein a range of said TDC covers less than a full range of said RF clock period.
A frequency synthesizer comprising:
- an oscillator for providing a variable clock;
- a phase shifter coupled to said oscillator, and arranged to provide a shifted variable clock whose phase is arranged to be different from phase of said variable clock by a phase offset, wherein said phase offset is such arranged that a time difference between a transition of a frequency reference clock and a prior transition of said shifted variable clock is less than a period of said variable clock;
- and
- a time-to-digital converter (TDC) coupled to said phase shifter, and arranged to provide a first fractional error correction signal by quantizing said time difference.
A frequency synthesizer comprising:
- an oscillator for providing a variable clock;
- a time-to-digital converter (TDC) arranged to provide a first fractional error correction signal by quantizing a time difference between a frequency reference clock and a shifted variable clock, wherein phase of said shifted variable clock is arranged to be different from phase of said variable clock by a phase offset;
- and
- a shift controller arranged to provide a second fractional error correction signal in response to an accumulated value of a frequency command word (FCW);
- wherein said oscillator is further arranged to tune periods of said variable clock according to said first fractional error correction signal and said second fractional error correction signal.
A method of synthesizing a frequency by providing a variable clock, comprising:
- generating said variable clock in response to an oscillator tuning signal;
- phase shifting said variable clock by a phase offset to obtain a shifted variable clock;
- and
- digitizing a timing difference of said shifted variable clock and a frequency reference clock such that a range of said digitizing covers less than a full range of said variable clock period.
Dependencies are inferred from the claim text.