Probe card partition scheme
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSandeep Kumar GOEL, Mill-Jer WANG
Life of this patent
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Abstract
A method of probe card partitioning for testing an integrated circuit die includes providing a first probe card partition layout having a first number of distinct sections. Each distinct section uses a distinct probe card for testing. The first probe card partition layout is repartitioned into a second probe card partition layout having a second number of distinct sections. The second number is less than the first number.
Claims20
A method of probe card partitioning for testing an integrated circuit die, comprising:
- providing a first probe card partition layout of the integrated circuit die having a first number of distinct sections, wherein each distinct section uses a distinct probe card for testing;
- and
- repartitioning the first probe card partition layout into a second probe card partition layout having a second number of distinct sections so that the second number is less than the first number.
A probe card partition layout, comprising:
- at least two sections or at least two contact patterns;
- and
- at least one alignment mark,
- wherein a first probe card is used for testing multiple sections of the at least two sections or for testing multiple contact patterns of the at least two contact patterns, and
- wherein the at least one alignment mark is used for tester alignment.
A method of probe card partitioning for testing an integrated circuit die, comprising:
- providing a test contact pattern for at least one section of a probe card partition layout of the integrated circuit die;
- arranging the test contact pattern into at least two contact patterns that are symmetric with respect to rotation by a specified angle;
- and
- providing a probe card partition layout having the at least two contact patterns.
Dependencies are inferred from the claim text.