Asymmetric MIM Capacitor for DRAM Devices
AssigneesElpida Memory, Inc., Intermolecular, Inc.
InventorsHanhong Chen, Hiroyuki Ode
Life of this patent
Estimating the term…
Abstract
A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO2 and RuO2. The capacitor stack including the bottom layer is subjected to a PMA treatment to reduce the oxygen vacancies in the dielectric layer and reduce the interface states at the dielectric/second electrode interface. The other component of the bilayer (i.e. top layer) is a high work function, high conductivity metal or conductive metal compound.
Claims20
A semiconductor layer stack comprising:
- a first electrode layer;
- a dielectric layer on the first electrode layer;
- and
- a bilayer second electrode structure on the dielectric layer, wherein the bilayer second electrode structure comprises a bottom layer on the dielectric layer and a top layer on the bottom layer, and wherein the bottom layer is crystallized.
A semiconductor layer stack comprising:
- a bottom layer, wherein the bottom layer comprises a conductive metal oxide;
- and
- a top layer formed on the bottom layer;
- wherein the bottom layer is crystallized.
Dependencies are inferred from the claim text.