Semiconductor device and method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, comprising:

• preparing a semiconductor substrate having a main surface;
• forming a first insulated gate field effect transistor including a pair of first source/drain regions formed on said main surface, and a first gate electrode formed on said main surface between said pair of first source/drain regions;
• forming a second insulated gate field effect transistor including a pair of second source/drain regions formed on said main surface, and a second gate electrode formed on said main surface between said pair of second source/drain regions;
• forming a bipolar transistor including an emitter region formed on said main surface, a base region formed on said main surface to form a pn junction with said emitter region, and a collector region formed on said main surface opposite to said emitter region relative to said base region to form a pn junction with said base region;
• forming a first element isolation structure on said main surface above the pn junction formed between said emitter region and said base region;
• forming a second element isolation structure on said main surface above the pn junction formed between said base region and said collector region;
• forming a third element isolation structure on said main surface opposite to said second element isolation structure relative to said collector region,
• forming a first dummy gate electrode, which is not used as a circuit, on an upper surface of at least one of said first element isolation structure, said second element isolation structure and said third element isolation structure;
• forming a protection film to cover said first insulated gate field effect transistor, said second insulated gate field effect transistor, said bipolar transistor and said first dummy gate electrode;
• patterning said protection film to expose said first insulated gate field effect transistor and said bipolar transistor;
• forming a metal film to cover said first insulated gate field effect transistor and said bipolar transistor exposed through said protection film and patterned said protection film;
• and
• subjecting said metal film to heat treatment to form a silicide film on each of said first source/drain regions, said emitter region, said base region and said collector region.