Three-dimensional semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJang-Gn YUN, Kwang Soo SEOL, Jungdal CHOI
Life of this patent
Estimating the term…
Abstract
Three-dimensional (3D) semiconductor memory devices are provided. According to the 3D semiconductor memory device, a gate structure includes gate patterns and insulating patterns alternately stacked on a semiconductor substrate. A vertical active pattern penetrates the gate structure. A gate dielectric layer is disposed between a sidewall of the vertical active pattern and each of the gate patterns. A semiconductor pattern is disposed on the gate structure and is connected to the vertical active pattern. A string drain region is formed in a portion of the semiconductor pattern and is spaced apart from the vertical active pattern.
Claims20
A three-dimensional (3D) semiconductor memory device comprising:
- a gate structure including gate patterns and insulating patterns alternately stacked on a semiconductor substrate;
- a vertical active pattern penetrating the gate structure;
- a gate dielectric layer disposed between a sidewall of the vertical active pattern and each of the gate patterns;
- a semiconductor pattern disposed on the gate structure, the semiconductor pattern connected to the vertical active pattern;
- and
- a string drain region formed in a portion of the semiconductor pattern, the string drain region spaced apart from the vertical active pattern.
A three-dimensional (3D) semiconductor memory device comprising:
- a first gate structure including first gate patterns and first insulating patterns alternately stacked on a semiconductor substrate;
- a first vertical active pattern penetrating the first gate structure;
- a second gate structure including second gate patterns and second insulating patterns alternately stacked on the semiconductor substrate, the second gate structure laterally spaced apart from the first gate structure;
- a second vertical active pattern penetrating the second gate structure;
- a gate dielectric layer disposed between a sidewall of each of the first and second vertical active patterns and each of the first and second gate patterns;
- a semiconductor pattern disposed on the first and second gate structures, the semiconductor pattern connected to the first and second vertical active patterns;
- and
- a string drain region disposed in the semiconductor pattern, the string drain region spaced apart from the first and second vertical active patterns.
A semiconductor memory device comprising:
- a gate structure including an insulating pattern and a gate pattern stacked on a substrate;
- a vertical active pattern penetrating the gate structure in a direction substantially perpendicular to a top surface of the substrate;
- and
- a semiconductor pattern disposed on top surfaces of the gate structure and the vertical active pattern, the semiconductor pattern including a string drain region, wherein the string drain region does not contact the vertical active pattern.
Dependencies are inferred from the claim text.