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US 2013/0092992 A1Published application
Replacement gate multigate transistor for embedded dram
AssigneeInternational Business Machines Corporation
InventorsJosephine B. Chang, Leland Chang, Michael A. Guillorn, Wilfried E. Haensch
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Abstract
A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
Claims20
A method for fabricating a memory cell transistor, the method comprising:
- forming a trench capacitor within a substrate;
- forming a non-planar transistor within the substrate;
- and
- forming a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
1 more element
A memory cell comprising:
- a trench capacitor;
- a non-planar transistor;
- and
- a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
1 more element
A memory array comprising:
- a plurality of DRAM memory cells, the DRAM memory cells each comprising:
- a trench capacitor;
- a non-planar transistor;
- and
- a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor;
- and
- a processor, wherein the processor and the plurality of DRAM cells are both formed in a monolithic silicon substrate.
4 more elements
Dependencies are inferred from the claim text.