Sharing a Check Bit Memory Device Between Groups of Memory Devices

A memory buffer device comprising:

• a first interface to communicate with first memory devices and a second interface to communicate with second memory devices, wherein the memory buffer transfers data via either the first interface or the second interface with the respective first or second memory devices;
• and
• a third interface for transferring error checking information corresponding to the data with a third memory device, wherein the memory buffer determines an error address indicating a location in the third memory device corresponding to the error checking information based on whether the data transfer is via the first interface or the second interface.

A memory controller comprising:

• a first interface to communicate with first memory devices and a second interface to communicate with second memory devices, wherein the memory controller transfers data via either the first interface or the second interface with the respective first or second memory devices;
• and
• a third interface to transfer error checking information corresponding to the data with a third memory device, wherein the memory controller determines an error address indicating a location in the third memory device corresponding to the error checking information based on whether the data transfer is via the first interface or the second interface.

A method of operation in a memory buffer device, the method comprising:

• receiving an indication of whether to transfer data with first memory devices or second memory devices;
• and
• responsive to the indication of whether to transfer data with the first memory devices or the second memory devices, determining an error address for transferring error checking information corresponding to the data, the error address indicating a location in a third memory device corresponding to the error checking information.