Cache and/or socket sensitive multi-processor cores breadth-first traversal
AssigneeIntel Corporation
InventorsNadathur Rajagopalan Satish, Changkyu Kim, Jatin Chhuagani, Jason D. Sewall
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AssigneeIntel Corporation
InventorsNadathur Rajagopalan Satish, Changkyu Kim, Jatin Chhuagani, Jason D. Sewall
Estimating the term…
Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are disclosed. In embodiments, a vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. In embodiments, potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. In various embodiments, the threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed. Other embodiments may be disclosed or claimed.
At least one computer-readable storage device having a plurality of instructions configured to enable a plurality of threads of an apparatus, in response to execution of a plurality of instances of the instructions by a plurality of processor cores of the apparatus, to:
A computer-implemented method comprising:
An apparatus comprising:
A system comprising:
Dependencies are inferred from the claim text.