US 2013/0075864 A1Published application

Semiconductor device

AssigneeSemiconductor Components Industries, LLC

InventorsSeiji OTAKE, Yasuhiro TAKEDA, Yuta MIYAMOTO

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Abstract

An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.

Claims8

Dependent claims

A semiconductor device comprising:

a semiconductor substrate of a first general conductivity type;
an epitaxial layer of a second general conductivity type formed on the semiconductor substrate;
a first buried layer of the second general conductivity type formed between the semiconductor substrate and the epitaxial layer so as to leave an opening in which a PN junction between the semiconductor substrate and the epitaxial layer is preserved;
a second buried layer of the first general conductivity type connected to a peripheral edge region of the first buried layer and extending from inside the semiconductor substrate into the epitaxial layer;
a first drawing layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be connected to the second buried layer;
a second drawing layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be surrounded by the second buried layer and the first drawing layer in plan view of the semiconductor substrate;
a first diffusion layer of the first general conductivity foamed in a surface portion of the epitaxial layer including the second drawing layer;
a second diffusion layer of the second general conductivity type connected to and surrounding the first diffusion layer in the plan view;
a cathode electrode connected to the first diffusion layer and the second diffusion layer;
and
an anode electrode connected to the first drawing layer,
wherein the first buried layer and the second buried layer are configured to form a PN junction diode,
the second drawing layer, the epitaxial layer and the semiconductor substrate are configured to form a parasitic bipolar transistor, or the second drawing layer, the epitaxial layer and the second buried layer are configured to form a parasitic bipolar transistor, and
the PN junction diode and the parasitic bipolar transistor are configured to form an ESD protection element.

11 more elements

A semiconductor device comprising:

a semiconductor substrate of a first general conductivity type;
an epitaxial layer of a second general conductivity type formed on the semiconductor substrate;
a first buried layer of the second general conductivity type formed between the semiconductor substrate and the epitaxial layer so as to leave an opening in which a PN junction between the semiconductor substrate and the epitaxial layer is preserved;
a second buried layer of the first general conductivity type connected to a peripheral edge region of the first buried layer and extending from inside the semiconductor substrate into the epitaxial layer;
a first drawing layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be connected to the second buried layer;
a first diffusion layer of the second general conductivity type formed in a surface portion of the epitaxial layer so as to be surrounded by the second buried layer and the first drawing layer in plan view of the semiconductor substrate;
a second drawing layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be connected to and surround the first diffusion layer in the plan view;
a cathode electrode connected to the first diffusion layer and the second drawing layer;
and
an anode electrode connected to the first drawing layer,
wherein the first buried layer and the second buried layer are configured to form a PN junction diode,
the second drawing layer, the epitaxial layer and the semiconductor substrate are configured to form a parasitic bipolar transistor, or the second drawing layer, the epitaxial layer and the second buried layer are configured to form a parasitic bipolar transistor, and
the PN junction diode and the parasitic bipolar transistor are configured to form an ESD protection element.

10 more elements

Dependencies are inferred from the claim text.