Semiconductor device with strained channels induced by high-k capping metal layers

A process of forming a semiconductor device with a metal gate stack, the process comprising:

• providing a semiconductor substrate;
• forming isolated NMOS and PMOS regions in the substrate;
• depositing a high-k (HK) dielectric layer over the semiconductor substrate;
• depositing a tensile stress HK capping layer on top of the HK dielectric layer on both of a NMOS region and a PMOS region;
• removing the tensile stress HK capping layer from the NMOS region;
• depositing a compressive stress N-work function (N-WF) metal layer over the HK layer on both of the NMOS and the PMOS regions;
• and
• depositing a stack of metal gate layers over the compressive stress N-WF metal layer.

A semiconductor device with a metal gate comprising:

• a semiconductor substrate;
• an interfacial layer (IL) formed over the semiconductor substrate;
• a high-k (HK) dielectric layer formed over the semiconductor substrate;
• a tensile stress HK capping layer formed over the IL in a PMOS region of the semiconductor substrate;
• a compressive stress HK capping layer formed over the IL in an NMOS region of the semiconductor substrate;
• and
• a stack of metal gate layers deposited over the HK capping layers;
• wherein the HK capping layers of the PMOS and NMOS regions are two different stress type layers;
• and
• wherein channels of the PMOS and NMOS regions are two different type strained channels.