Structures and methods of self-aligned gate for sb-based fets
OwnerHan-Chieh Ho, Heng-Kuang Lininventors
Life of this patent
Estimating the term…
Abstract
The advantage of narrow-bandgap Sb-based devices is the realization of high-frequency operation with much lower power consumption. However, some properties such as chemical stability are the key issues for developing Sb-based devices. The process temperature of the ion implant and thermal annealing in conventional silicon industry is over 1000° C. Sb-based materials are easily degraded at temperature greater 300° C. Thus, this invention provides three processes for self-aligned gate with lower process temperature (<300° C.) to reduce device access region resistance and maintain material quality.
Claims20
A structure of Sb-based FETs, comprising:
- a Sb-based epitaxial layer, which comprises a buffer layer, a channel layer and a gate dielectric layer, wherein said channel layer is formed on said buffer layer and said gate dielectric layer is formed on said channel layer;
- a gate metal layer formed on said gate dielectric layer;
- a spacer formed on said gate dielectric layer;
- and
- a passivation layer formed on said gate metal layer, wherein said gate metal layer, said spacer and said passivation layer construct a self-aligned gate.
A structure of Sb-based FETs, comprising:
- a Sb-based epitaxial layer, which comprises a buffer layer, a channel layer and a gate dielectric layer, wherein said channel layer is formed on said buffer layer and said gate dielectric layer is formed on said channel layer;
- a gate metal layer formed on said dielectric layer;
- and
- a second dielectric layer formed on said gate metal layer, wherein said gate metal layer and said second dielectric layer construct a self-aligned gate, wherein said self-aligned gate has the same region with that of said channel layer and said gate dielectric layer
A method for fabricating Sb-based FETs, comprising:
- forming a patterned first photo resist layer on a Sb-based epitaxial layer to create an opening, wherein said Sb-based epitaxial layer comprises a buffer layer, a channel layer and a gate dielectric layer, wherein said channel layer is formed on said buffer layer and said gate dielectric layer is formed on said channel layer;
- forming a second dielectric layer to cover upper surface and sidewall of said patterned first photo resist layer and upper surface of said Sb-based epitaxial layer below said opening;
- selectively removing said second dielectric layer to form a spacer on sidewall of said patterned first photo resist layer;
- forming a metal material layer on said patterned first photo resist layer and said spacer to cover said patterned first photo resist layer, and fill into said opening;
- selectively removing said metal material layer to form a gate metal layer on said Sb-based epitaxial layer and connect to sidewall of said spacer;
- forming a third dielectric layer on said patterned first photo resist layer, said spacer and said gate metal layer;
- selectively removing said third dielectric layer to form a gate passivation layer on said gate metal layer;
- and
- removing said patterned first photo resist layer to form a self-aligned gate.
A method for fabricating Sb-based FETs, comprising:
- forming a metal layer on a Sb-based epitaxial layer, wherein said Sb-based epitaxial layer comprises a buffer layer, a channel layer and a gate dielectric layer, wherein said channel layer is formed on said buffer layer and said gate dielectric layer is formed on said channel layer;
- forming a first dielectric layer on said metal layer;
- and
- removing said first dielectric layer, said metal layer and said Sb-based epitaxial layer except gate area to form a gate structure and expose said channel layer.
Dependencies are inferred from the claim text.