Semiconductor device and method of manufacturing the same
AssigneeElpida Memory, Inc.
InventorsSatoshi KATAGIRI, Kenji MAE
Life of this patent
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Abstract
A semiconductor device includes a plurality of first memory cells, at least one of second memory cells, and a control circuit. The plurality of first memory cells are accessed during normal operation, wherein the first memory cell includes a first variable resistance element. The second memory cell is not accessed during the normal operation but accessed at a time of test operation. The second memory cell includes a second variable resistance element practically identical to the first variable resistance element. The control circuit performs forming on the second memory cell at the time of the test operation.
Claims19
A semiconductor device comprising:
- a plurality of first memory cells that are accessed during normal operation, wherein each of the first memory cells includes a first variable resistance element;
- at least one second memory cell that is not accessed during said normal operation but accessed at a time of test operation, wherein said at least one second memory cell includes a second variable resistance element practically identical to said first variable resistance element;
- and
- a control circuit that performs forming on said at least one second memory cell at the time of said test operation.
A method of manufacturing a semiconductor device, wherein said semiconductor device includes first variable resistance memory cells that operate as a memory during normal operation and a plurality of second variable resistance memory cells that are used for a forming for acquiring forming condition, said method comprising:
- performing a forming control for said plurality of second variable resistance memory cells by different conditions from each other;
- detecting whether or not each of said plurality of second variable resistance memory cells transits to a first resistance state after said forming control;
- and
- performing a forming control for said first variable resistance memory cells based on a condition of one(s) among said plurality of second variable resistance memory cells that transits to said first resistance state as a result of said detection.
A system, comprising:
- a semiconductor device that includes:
- a first memory circuit including a plurality of normal and redundancy memory cells each including a variable resistance element;
- a second memory circuit including at least one test memory cell including the variable resistance element;
- and
- a controller coupled to said semiconductor device, said controller being configured to perform a read/write operation on said first memory circuit of said semiconductor device and not to perform the read/write operation on said second memory circuit.
Dependencies are inferred from the claim text.