System and methods for converting planar design to finfet design
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsClement Hsingjen WANN, Chih-Sheng CHANG, Yi-Tang LIN, Ming-Feng SHIEH
Life of this patent
Estimating the term…
Abstract
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
Claims20
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, said method comprising:
- receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas and planar dummy areas;
- defining a plurality of FinFET active areas and FinFET dummy areas corresponding to the planar active areas and planar dummy areas;
- defining a plurality of FinFET boundaries, each FinFET boundary including one or more FinFET active areas;
- generating a plurality of mandrels for the plurality of FinFET active areas and FinFET dummy areas;
- for each FinFET boundary, generating a dummy mandrel parallel to the generated mandrels on top and/or bottom of a FinFET boundary if a space between the FinFET boundary and an adjacent feature is greater than a dummy mandrel insertion spacing;
- and
- for each FinFET boundary, extending one or both ends of the generated mandrels;
- outputting a FinFET structure layout.
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, said method comprising:
- receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas and planar dummy areas;
- defining a plurality of FinFET active areas and FinFET dummy areas corresponding to the planar active areas and planar dummy areas;
- defining a plurality of FinFET boundaries, each FinFET boundary including one or more FinFET active areas;
- generating a plurality of mandrels for the plurality of FinFET boundaries;
- for each FinFET boundary having different length mandrels, lengthening one or more short mandrels adjacent to a long mandrel until all mandrels in one FinFET boundary have a same length or a space between one or both ends of the one or more short mandrels and an adjacent feature reaches a minimum spacing;
- generating a plurality of mandrels for the plurality of FinFET dummy areas until a distance between end mandrels of the mandrels in a FinFET dummy area and an adjacent feature is less than the dummy mandrel insertion spacing;
- and
- outputting a FinFET structure layout.
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, said method comprising:
- receiving a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas and planar dummy areas;
- defining a plurality of FinFET active areas and FinFET dummy areas corresponding to the planar active areas and planar dummy areas;
- defining a plurality of FinFET boundaries, each FinFET boundary including one or more FinFET active areas;
- generating a plurality of mandrels for the plurality of FinFET boundaries and the plurality of FinFET dummy areas;
- inserting global dummy mandrels in empty areas of the FinFET structure layout wherein end mandrels of the global dummy mandrels are separated from nearest features by at least a specified dummy mandrel minimum spacing and wherein the mandrel ends of the global dummy mandrels are separated from nearest feature by at least a specified dummy mandrel end minimum spacing;
- and
- outputting the FinFET structure layout.
Dependencies are inferred from the claim text.