US 2012/0278771 A1 · Logic modification synthesis for high performance circuits

Abstract

A method for IC modification is disclosed. The method recognizes an original HDL file prescribing an original logic, an original netlist incorporating the original logic, and a new HDL file prescribing a new logic. The new logic comprises desired logic changes relative to the original logic. If a signal is different between the new HDL file and the original HDL file the method adds a user hint to both the original HDL file and the new HDL file. Using the original HDL file, the original netlist, the new HDL file, and the user hints, the method synthesizes a delta netlist for inserting into the original netlist, whereupon this insertion the original netlist will incorporate the new logic.

Claims15

Dependent claims

A method, comprising:

recognizing an original hardware description language (HDL) file prescribing an original logic;
recognizing an original netlist incorporating said original logic;
recognizing a new HDL file prescribing a new logic, wherein said new logic comprises a desired logic change relative to said original logic, wherein said original HDL file and said new HDL file both comprise signals;
adding a user hint to both said original HDL file and said new HDL file when one of said signals is different between said new HDL file and said original HDL file;
synthesizing a delta netlist using said original HDL file, said original netlist, said new HDL file, and said user hint;
and
inserting said delta netlist into said original netlist, whereupon said original netlist is incorporating said new logic.

4 more elements

A computer program product comprising a computer readable storage medium having a computer readable program code embodied therewith, wherein said computer readable program code when executed on a computer causes said computer to:

recognize an original hardware description language (HDL) file prescribing an original logic;
recognize an original netlist incorporating said original logic;
recognize a new HDL file prescribing a new logic, wherein said new logic comprises a desired logic change relative to said original logic, wherein said original HDL file and said new HDL file both comprise signals;
add a user hint to both said original HDL file and said new HDL file when one of said signals is different between said new HDL file and said original HDL file;
synthesize a delta netlist using said original HDL file, said original netlist, said new HDL file, and said user hint;
and
insert said delta netlist into said original netlist, whereupon said original netlist is incorporating said new logic.

4 more elements

Dependencies are inferred from the claim text.

Logic modification synthesis for high performance circuits

Life of this patent

Logic modification synthesis for high performance circuits

Life of this patent

Abstract

Claims15