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US 2012/0269023 A1Published application
System with controller and memory
AssigneeElpida Memory, Inc.
InventorAtsuo KOSHIZUKA
Life of this patent
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Abstract
According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
Claims14
A system comprising:
- a controller comprising first, second and third terminals provided independently of each other;
- and
- a memory comprising fourth, fifth and sixth terminals provided independently of each other and provided correspondingly to the first, second and third terminals of the controller;
- the controller being configured to output a write data signal to the third terminal while the controller is clocking the first terminal and the memory being configured to receive the write data signal from the sixth terminal while the fourth terminal is being clocked in response to the clocking the first terminal;
- the memory being configured to output a read data signal to the sixth terminal while the memory is clocking the fifth terminal and the controller being configured to receive the read data signal from the third terminal while the second terminal is being clocked in response to the clocking the fifth terminal, the memory being configured to clock the fifth terminal while the fourth terminal is being clocked, and the fourth terminal is being clocked while the controller is clocking the first terminal.
2 more elements
A system comprising:
- a controller including;
- first, second, third, fourth and fifth terminals provided independently of each other;
- a clock generator supplied with a clock signal, generating a first signal based on the clock signal, outputting the first signal to the first terminal, generating a second signal based on the clock signal, and outputting the second signal to the second terminal;
- a command control circuit generating a command signal and outputting the command signal to the third terminal in synchronization with the first signal;
- and
- a data control circuit generating a first data signal and outputting the first data signal to the fourth terminal in synchronization with the second signal;
- and
- a memory including;
- sixth, seventh, eighth, ninth and tenth terminals provided independently of each other and coupled respectively to the first, second, third, fourth and fifth terminals of the controller;
- a signal generator receiving the second signal from the seventh terminal to generate a third signal and outputting the third signal to the tenth terminal;
- and
- an additional data control circuit generating a second data signal and outputting the second data signal to the ninth terminal in synchronization with the third signal.
9 more elements
Dependencies are inferred from the claim text.