Memory system having memory and memory controller and operation method thereof
OwnerSang-Hoon SHIN, Tae-Yong LEEinventors
Life of this patent
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Abstract
An operation method of a memory system including a memory and a memory controller includes transmitting defective-cell address information to the memory controller from the memory at an initial operation of the memory, wherein the defective-cell address information includes an address of a defective cell of the memory, and accessing, by the memory controller, an area of the memory excluding an area indicated by the defective-cell address information inside the memory.
Claims18
An operation method of a memory system including a memory and a memory controller, comprising:
- transmitting defective-cell address information to the memory controller from the memory at an initial operation of the memory, wherein the defective-cell address information includes an address of a defective cell of the memory;
- and
- accessing, by the memory controller, an area of the memory excluding an area indicated by the defective-cell address information inside the memory.
A memory system comprising:
- a memory comprising a plurality of data storage units configured to store data and a defective-cell address information storage unit configured to store defective-cell address information;
- and
- a memory controller configured to control the memory, receive the defective-cell address information from the memory, and read or write data from or into the data storage units of the memory excluding a unit indicated by the defective-cell address information among the plurality of data storage units.
An operation method of a memory controller, comprising:
- receiving defective-cell address information from a memory;
- storing the received defective-cell address information;
- and
- accessing an area of the memory to perform a read/write operation other than an area indicated by the defective-cell address information inside the memory.
An operation method of a memory system including a memory and a memory controller, comprising:
- applying a test command to the memory from the memory controller;
- generating defective-cell address information by testing the memory in response to the test command;
- storing the defective-cell address information in the memory controller;
- and
- accessing, by the memory controller, an area of the memory excluding an area indicated by the defective-cell address information inside the memory.
A memory controller comprising:
- a defect storage unit configured to store defective-cell address information of the memory;
- and
- a control unit configured to access an area of the memory excluding a data storage unit indicated by the defective-cell address information among a plurality of data storage units of the memory.
Dependencies are inferred from the claim text.